This article contains information about Intel's GPUs (see Intel Graphics Technology) and motherboard graphics chipsets in table form. In 1982, Intel licensed the NEC μPD7220 and announced it as the Intel 82720 Graphics Display Controller.[1][2]
First generation
Intel's first generation GPUs:
Second generation
Intel marketed its second generation using the brand Extreme Graphics. These chips added support for texture combiners allowing support for OpenGL 1.3.
Third generation
Intel's first DirectX 9 GPUs with hardware Pixel Shader 2.0 support.
Gen4
The last generation of motherboard integrated graphics. Full hardware DirectX 10 support starting with GMA X3500.
Each EU has a 128-bit wide FPU that natively executes four 32-bit operations per clock cycle.
Gen5
Integrated graphics chip moved from motherboard into the processor.
Improved gaming performance
Can access CPU's cache
Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle.[20]
Hierarchical-Z compression and fast Z clear[21]
Gen6
Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle.[20]
Double peak performance per clock cycle compared to previous generation due to fused multiply-add instruction.[20]
The entire GPU shares a sampler and an ROP.[20]
Gen7
1 FP32 ALUs : EUs : Subslices
Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions.
Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.
Gen8
1 FP32 ALUs : EUs : Subslices
Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions is one per 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
Each Subslice contains 8 EUs and a sampler (4 tex/clk[48]), and has 64 KB shared memory.
For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT.
Gen9
1 FP32 ALUs : EUs : Subslices
Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter (eighth in Apollo Lake) of the FP32 FLOPS.
Each Subslice contains 8 EUs (two of which are disabled in GT1) and a sampler (4 tex/clk), and has 64 KB shared memory.
For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT.
Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
Each Subslice contains 8 EUs and a sampler (4 tex/clk), and has 64 KB shared memory.
^ shading cores (ALU):texture mapping units (TMU):render output units (ROP):ray tracing units:tensor cores (XMX):execution Units
^ Boost values (if available) are stated below the base value in italic.
^ Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
^ Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
Gen 12.7
Desktop
v
t
e
^ Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units (tensor cores (XMX): execution units: render slices)
^ Boost values (if available) are stated below the base value in italic.
Mobile
v
t
e
^ Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units (tensor cores (XMX): execution units: render slices)
^Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
^ Boost values (if available) are stated below the base value in italic.
^Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
Workstation
v
t
e
^ Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units (tensor cores (XMX): execution Units: render slices)
^ Boost values (if available) are stated below the base value in italic.
^ Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
^ Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
The raw performance of integrated GPU, in FLOPS, can be calculated as follows:
For example, the HD Graphics 3000 is rated at 125 GFLOPS,[110] which is consistent with the formula (12 * 4 * 2 * 1,300 MHz).
References
^Antognetti, P.; Anceau, F.; Vuillemin, J. (6 December 2012). Microarchitecture of VLSI Computers. Springer Science & Business Media. ISBN 9789400951433.
^ a b c d e f"Intel Graphics — Built for mainstream Desktop and Mobile PC Users" (PDF). Archived from the original (PDF) on 2007-11-28. Retrieved 2007-06-08.
^ a b"Intel 3 Series Chipsets Datasheet" (PDF). Retrieved 2009-10-17.
^"Mobile Intel 945 Express Chipset,Intel DVMT 3.0" (PDF). Archived from the original (PDF) on July 11, 2009. Retrieved 2010-10-01.
^"Intel Atom Processors" (PDF). Intel.com. Retrieved 2017-03-21.
^ a b c d e f g"mesa/mesa - The Mesa 3D Graphics Library". freedesktop.org. Retrieved 2017-08-07.
^ a b c"Intel's Next Generation Integrated Graphics Architecture – Intel Graphics Media Accelerator X3000 and 3000" (PDF). Retrieved 2007-06-08.
^ a b"Intel G35 Product Brief" (PDF). Download.intel.com. Retrieved 2009-09-17.
^"Intel GMA 3000 and X3000 Developer's Guide". Software.intel.com. Retrieved 2012-09-21.
^ a b c"Mobile Intel 965 Express Chipset Family Datasheet" (PDF). Download.intel.com. Retrieved 2017-03-21.
^ a b"Intel 4 Series Chipset Family Datasheet" (PDF). Intel.com. Retrieved 2009-09-17.
^ a b c"Mobile Intel(R) 4 Series Express Chipset Family Datasheet" (PDF). Intel.com. Archived from the original (PDF) on 2008-10-31. Retrieved 2009-09-17.
^ a b c dKanter, David (2011-08-08). "Intel's Sandy Bridge Graphics Architecture". real world technologies. Retrieved 21 March 2017.
^"-NEW- Intel Iris, Iris Pro, and HD Graphics Production Driver for Windows* 10 64-bit 15.40.4.64.4256". intel.com. 29 July 2015. Retrieved 21 March 2017.
^Supported with Mesa Crocus driver. Legacy i965 driver only supports up to OpenGL 4.5.
^Supported with Mesa Crocus driver. Legacy i965 driver only supports up to OpenGL ES 3.1.
^ a b c d"Vulkan 1.1 Support Lands In Mesa Git For RADV, ANV - Phoronix". www.phoronix.com. Retrieved 2018-08-09.
^ a b c d"Intel(R) Graphics Compute Runtime for OpenCL(TM)". GitHub. Retrieved 2019-11-08.
^Atom x5-Z8350 info retrieved from http://ark.intel.com/products/93361/Intel-Atom-x5-Z8350-Processor-2M-Cache-up-to-1_92-GHz as well as editors' hardware.
^"WDDM 2.2 on Skylake?". intel. 19 August 2017. Retrieved 2017-10-14.
^ a b"mesa/mesa - The Mesa 3D Graphics Library". freedesktop.org. Retrieved 2017-08-08.
^ a b"mesa/mesa - The Mesa 3D Graphics Library". freedesktop.org. Retrieved 2017-08-08.
^"Intel Data Center GPU Max Series Overview". Intel. Retrieved 13 September 2023.
^"Intel® Data Center GPU Max Series Product Brief" (PDF). Intel. 2023-08-15. Retrieved 2023-11-03. Based on the Xe HPC architecture that uses both EMIB 2.5D and Foveros packaging technologies to combine 47 active tiles onto a single GPU, fabricated on five different process nodes, Intel Max Series GPUs enable greater flexibility and modularity in the construction of the SOC.
^"Intel Arc Graphics". Intel. Retrieved December 23, 2022.
^"Intel Arc Graphics". Intel.
^ a b c d e"Intel® Arc™ Pro A-Series Graphics". Intel.
^"Intel 946 Express Chipset Family Datasheet" (PDF). Intel.com. Retrieved 2009-09-17.
^"VR-Zone : Technology Beats — Intel GM47 Mobile Chipset Delivers 2X Graphics Performance". Sg.vr-zone.com. 2008-02-25. Archived from the original on 2008-12-02. Retrieved 2009-09-17.
^"Factsheet and white paper downloads - Imagination Technologies" (PDF). imgtec.com. Retrieved 21 March 2017.[permanent dead link]
^"Intel Atom Processor Z670 (512K Cache, 1.50 GHz) Product Specifications". intel.com. Retrieved 21 March 2017.
^"Intel Atom Processor Z2460" (PDF). Download.intel.com. Retrieved 2017-03-21.
^ a b"Archived copy" (PDF). Archived from the original (PDF) on 2012-02-27. Retrieved 2012-03-02.{{cite web}}: CS1 maint: archived copy as title (link)
