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Processor register

A register-transfer level (RTL) description of a 8-bit register with detailed implementation, showing how 8 bits of data can be stored by using Flip-flops.

A processor register is a quickly accessible location available to a computer's processor.[1] Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. In computer architecture, registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.[2]

Almost all computers, whether load/store architecture or not, load items of data from a larger memory into registers where they are used for arithmetic operations, bitwise operations, and other operations, and are manipulated or tested by machine instructions. Manipulated items are then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels.

Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The term normally refers only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. However, modern high-performance CPUs often have duplicates of these "architectural registers" in order to improve performance via register renaming, allowing parallel and speculative execution. Modern x86 design acquired these techniques around 1995 with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.

When a computer program accesses the same data repeatedly, this is called locality of reference. Holding frequently used values in registers can be critical to a program's performance. Register allocation is performed either by a compiler in the code generation phase, or manually by an assembly language programmer.

Size

Registers are normally measured by the number of bits they can hold, for example, an "8-bit register", "32-bit register", "64-bit register", or even more. In some instruction sets, the registers can operate in various modes, breaking down their storage memory into smaller parts (32-bit into four 8-bit ones, for instance) to which multiple data (vector, or one-dimensional array of data) can be loaded and operated upon at the same time. Typically it is implemented by adding extra registers that map their memory into a larger register. Processors that have the ability to execute single instructions on multiple data are called vector processors.

Types

A processor often contains several kinds of registers, which can be classified according to the types of values they can store or the instructions that operate on them:

Hardware registers are similar, but occur outside CPUs.

In some architectures (such as SPARC and MIPS), the first or last register in the integer register file is a pseudo-register in that it is hardwired to always return zero when read (mostly to simplify indexing modes), and it cannot be overwritten. In Alpha, this is also done for the floating-point register file. As a result of this, register files are commonly quoted as having one register more than how many of them are actually usable; for example, 32 registers are quoted when only 31 of them fit within the above definition of a register.

Examples

The following table shows the number of registers in several mainstream CPU architectures. Note that in x86-compatible processors, the stack pointer (ESP) is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.

Although all of the below-listed architectures are different, almost all are in a basic arrangement known as the von Neumann architecture, first proposed by the Hungarian-American mathematician John von Neumann. It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs.

Usage

The number of registers available on a processor and the operations that can be performed using those registers has a significant impact on the efficiency of code generated by optimizing compilers. The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.

See also

References

  1. ^ "What is a processor register?". Educative: Interactive Courses for Software Developers. Retrieved 2022-08-12.
  2. ^ "A Survey of Techniques for Designing and Managing CPU Register File".
  3. ^ "Cray-1 Computer System Hardware Reference Manual" (PDF). Cray Research. November 1977. Archived (PDF) from the original on 2021-11-07. Retrieved 2022-12-23.
  4. ^ "MCS-4 Micro Computer Set Users Manual" (PDF). Intel. February 1973.
  5. ^ "8008 8 Bit Parallel Central Processor Unit Users Manual" (PDF). Intel. November 1973. Retrieved January 23, 2014.
  6. ^ "Intel 8080 Microcomputer Systems User's Manual" (PDF). Intel. September 1975. Retrieved January 23, 2014.
  7. ^ "80286 and 80287 Programmer's Reference Manual" (PDF). Intel. 1987.
  8. ^ a b "Intel 64 and IA-32 Architectures Software Developer Manuals". Intel. 4 December 2019.
  9. ^ "AMD64 Architecture Programmer's Manual Volume 1: Application Programming" (PDF). AMD. October 2013.
  10. ^ "Intel Architecture Instruction Set Extensions and Future Features Programming Reference" (PDF). Intel. January 2018.
  11. ^ F8 Guide to Programming (PDF). Fairchild MOS Microcomputer Division. 1977.
  12. ^ "Nios II Classic Processor Reference Guide" (PDF). Altera. April 2, 2015.
  13. ^ "Nios II Gen2 Processor Reference Guide" (PDF). Altera. April 2, 2015.
  14. ^ "M6800 Programming Reference Manual" (PDF). Motorola. November 1976. Retrieved May 18, 2015.
  15. ^ "Motorola M68000 Family Programmer's Reference Manual" (PDF). Motorola. 1992. Retrieved June 13, 2015.
  16. ^ "CUDA C Programming Guide". Nvidia. 2019. Retrieved Jan 9, 2020.
  17. ^ Jia, Zhe; Maggioni, Marco; Staiger, Benjamin; Scarpazza, Daniele P. (2018). "Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking". arXiv:1804.06826 [cs.DC].
  18. ^ "IBM Enterprise Systems Architecture/370 and System/370 - Vector Operations" (PDF). IBM. SA22-7125-3. Retrieved May 11, 2020.
  19. ^ "IBM S/390 G5 Microprocessor" (PDF).
  20. ^ "MMIX Home Page".
  21. ^ "Series 32000 Databook" (PDF). National Semiconductor.
  22. ^ "Synergistic Processor Unit Instruction Set Architecture Version 1.2" (PDF). IBM. January 27, 2007.
  23. ^ "Learning 65816 Assembly". Super Famicom Development Wiki. Retrieved 14 November 2019.
  24. ^ "Procedure Call Standard for the ARM Architecture" (PDF). ARM Holdings. 30 November 2013. Retrieved 27 May 2013.
  25. ^ "2.6.2. The Thumb-state register set". ARM7TDMI Technical Reference Manual. ARM Holdings.
  26. ^ "Procedure Call Standard for the ARM 64-bit Architecture" (PDF). ARM Holdings. 22 May 2013. Retrieved 27 May 2013.
  27. ^ "Epiphany Architecture Reference" (PDF).